Systems and methods for accessing memory

ABSTRACT

Methods of mapping memory cells to applications, methods of accessing memory cells, systems, and memory controllers are described. In some embodiments, a memory system including multiple physical channels is mapped into regions, such that any region spans each physical channel of the memory system. Applications are allocated memory in the regions, and performance and power requirements of the applications are associated with the regions. Additional methods and systems are also described.

PRIORITY APPLICATION

This application is a divisional of U.S. application Ser. No.13/746,141, filed Jan. 21, 2013, which is incorporated herein byreference in its entirety.

BACKGROUND

Memory systems are used in many electronic devices such as personaldigital assistants (PDAs), laptop computers, mobile phones and digitalcameras. Some of these memory systems include multiple physical channelshaving physical pins for communicating with memory cells of the memorysystem. With some memory mapping schemes, memory maps are generated tomap logical addresses of applications using the memory system to thephysical channels of the memory system. Portions of one or more of themultiple physical channels may be mapped based on the performancerequirements or power requirements of the application that will berunning in that memory space. As applications are started or terminated,gaps may be generated in the memory map and it may become increasinglydifficult to find available regions in the memory system to suit theneeds of any newly started applications.

Some other memory mapping schemes have been proposed to map one or morephysical channels to a processor or group of processors, where eachchannel provides the same performance point or power specifications.While gaps may be avoided, such a homogeneous scheme may not meet theneeds of processors with varying performance or power requirements.

BRIEF DESCRIPTION OF THE DRAWINGS

Some embodiments of the disclosed technology are illustrated by way ofexample and not limitation in the figures of the accompanying drawingsin which:

FIG. 1 is a diagram of a system according to various embodiments;

FIG. 2 is a diagram of a memory system according to various embodiments;

FIG. 3 is a diagram of address mappings according to variousembodiments;

FIG. 4 is a flow diagram illustrating a method for mapping addressesaccording to various embodiments;

FIG. 5 is a flow diagram illustrating a method for performingtransactions on memory cells according to various embodiments;

FIG. 6 is a diagram of an address configured according to an addressingmethod according to various embodiments;

FIG. 7 is a diagram of an address configured according to anotheraddressing method according to various embodiments; and

FIG. 8 is a flow diagram illustrating a method for allocating memoryaccording to various embodiments.

DETAILED DESCRIPTION

FIG. 1 is a diagram illustrating a system 100 for mapping and accessingmemory cells in a multi-channel memory system according to variousembodiments. The system 100 may include a processor 110 coupled to amemory controller 115 through a first bus 120. The memory controller 115may be coupled to a memory system 125 through a second bus 130. Thememory controller 115 may execute memory transaction requests from theprocessor 110. The memory controller 115 transfers data between theprocessor 110 and the memory system 125 over the first and second buses120 and 130. The first bus 120 and the second bus 130 may employ a knownprotocol to connect the processor 110 to the memory controller 115 andto connect the memory controller 115 to the memory system 125. Someexamples of system 100 may include personal computers, laptop computers,personal digital assistants (PDAs), digital cameras, electronic games,digital media player/records, and the like.

The memory system 125 may comprise one or more physical devices (notshown) each comprised of one or more physical channels (not shown) thatare mapped to regions according to a data structure, hereinafterreferred to by example as a “table”, stored in a map RAM 140 in thememory controller 115. The memory system 125 and the relationshipbetween physical devices and physical channels are described in moredetail below with respect to FIG. 2. The table may further beredundantly stored on a second map RAM (not shown) of the memorycontroller 115. The one or more map RAMs 140 may be, for example, staticrandom-access memory (SRAM).

The processor 110 may also be referred to as a master, and there may bemore than one master in system 100. An operating system (OS) 150 and oneor more applications 160 may execute on the processor 110. The OS 150may request memory in the memory system 125 on behalf of the one or moreapplications 160. The OS 150 may program a start address and an endaddress that define a region of the memory system to be mapped to theapplication 160 in the map RAM 140. The OS 150 may further programchannel depth values for the regions of the memory system in the map RAM140.

In other embodiments, the memory controller 115 may be co-located withthe processor 110. In embodiments, the processor 110 may be asystem-on-chip (SOC) and the processor 110 may use the memory controller115 to perform memory operations on the memory system 125.

The system 100 may include a machine-readable medium on which is storedone or more sets of instructions 180 (e.g., software) embodying any oneor more of the methodologies or functions described herein. Theinstructions 180 may reside, completely or at least partially, withinthe processor 110 or the memory controller 115 during execution thereofby the system 100, with the processor 110 and the memory controller 115also constituting machine-readable media.

The machine-readable medium may be a single medium or may be multiplemedia (e.g., a centralized or distributed database, and/or associatedcaches and servers) that store the one or more sets of instructions.“Machine-readable medium” may include any non-transitory medium that iscapable of storing, encoding, or carrying a set of instructions ofexecution by the machine. By way of example and not limitation,“machine-readable medium” may include solid-state memories, opticalmedia, or magnetic media.

FIG. 2 is a block diagram of a memory system 125 according to variousembodiments. In the illustrative example, the memory system 125comprises physical channels 210-1 through 210-8 arranged in parallel. Aphysical channel can comprise a set of physical pins (not shown) used tocommunicate with the corresponding memory cells in memory banks B0-Bb ofthe memory system 125. A physical device may include one or morephysical channels. Examples of physical devices may include dynamicrandom access memory (DRAM) devices, synchronous dynamic random accessmemory (SDRAM) devices and Flash memory devices. Hereinafter, the term“physical channel” may be interpreted to mean either a physical channelof a single-channel physical device, a physical channel of amulti-channel physical device, or a physical channel of multiplephysical devices. The memory system 125 may comprise any natural numberN of physical devices and therefore any number M of physical channels,where M is a natural number multiple of N. As shown, an OS page may spanacross each of the physical channels 210-1 through 210-8. The OS page isdescribed in more detail below with respect to FIG. 3. Each of thephysical channels 210-1 through 210-8 may be placed in a plan other thanthe parallel arrangement shown in FIG. 2.

The memory controller 115 may convert addresses received from aprocessor 110 into device address signals according to address mappingschemes. These device address signals may include bank, row and columnaddress signals for accessing desired portions of physical memory in thememory system 125.

Some memory controllers, for example, may implement an address mappingscheme to map addresses across a subset of physical channels of asystem, so that a region mapped to one particular application may spanacross, for example, two of eight physical channels, while a regionmapped to a different application may span across four more of the eightphysical channels. Further, the different applications may have varyingmemory requirements and therefore the mapped regions will comprisevarying numbers of rows of memory cells. While mapping the regions inthis way will allow different applications to operate at differentperformance points or under different power usage profiles by allowingthe physical channels to be configured at different channel depths fordifferent applications, unfillable gaps may be generated in the memorymap as applications are started and stopped. For example, a gap of acertain width and comprising a certain number of memory pages may beunusable unless an application is later initiated that requires thatparticular interface width or amount of memory.

Embodiments provide non-homogeneous memory mapping methods adapted topermit different memory performance points for different applicationswithout leaving inefficient gaps in the memory map. FIG. 3 is diagram ofan example map that may be created when mapping methods are implementedin accordance with some embodiments. As an illustrative example, the OS150 may map a region 310 of the memory system to a requesting process,such as an application 160 requiring memory in the amount of three OSpages. Each OS page spans across the physical channels 210-1 through210-8 to include at least a respective portion of each of the physicalchannels 210-1 through 210-8. In embodiments, an OS page includes thesame row in each of the physical channels 210-1 through 210-8. Each OSpage includes an amount of memory equal to the number of physicalchannels 210-1 through 210-8 multiplied by the number of banks in eachphysical channel 210-1 through 210-8, and further multiplied by thenumber of bytes in, for example, a DRAM page (typically on the order of256 kilobytes or 512 kilobytes).

According to embodiments, the OS 150 may allocate a natural numbermultiple of OS pages to subsequent applications 160. A region cancorrespond to rows of memory cells and rows in the memory map.Therefore, assuming that the requested amount of memory is available inthe memory system 125, regardless of the I/O width or channel depthneeds of an application 160, an appropriate number of OS pages may beallocated by the OS 150 based on the memory requirements of requestingapplications without generating unfillable gaps over time. Theappropriate number of OS pages is thereby mapped to the correspondingapplication 160. Using the region definitions, such as the data valuesstored in association with physical starting and ending addresses ofthese regions and channel depths of these regions, as described in moredetail below, the memory controller 115 may control memory transactionsaccording to performance and/or power requirements of the individualapplications 160.

FIG. 4 is a flow diagram illustrating a method of mapping a memorysystem having two or more physical channels according to variousembodiments. In embodiments, concurrently or in association withapplication 160 startup or initialization, an application 160 mayrequest a certain amount of memory, hereinafter a memory allocation,from the OS 150. The OS 150 examines the table stored in the map RAM 140to determine starting and ending addresses of an available portion ofthe memory that has the desired size. The OS 150 stores a startingaddress and an ending address for the application 160, in the table,defining a region of the memory system. The region will comprise therequested size of memory, in natural number multiples of OS pages, suchthat each OS page includes at least a respective portion of eachphysical channel 210-1 through 210-8. The OS 150 programs the startingaddress and ending address for the region into a table in the map RAM140 thereby mapping, in operation 410, the region to a logical memory ofa requesting process, e.g., the application 160. The region is mapped bythe OS 150 to include the same rows of memory cells in each of thephysical channels 210-1 through 210-8. The region will not necessarilycomprise contiguous OS pages within the memory system. Non-contiguous OSpages are described in more detail below with respect to FIG. 3.

The OS 150 may store a value associated with the region in the table inthe map RAM 140. The value may indicate a number of bytes to be accessedfrom each of the two or more physical channels before an address mappedto the region increments into a different channel. This value may beknown as a “channel depth,” described in more detail below.

In some embodiments, the application 160 may further notify the OS 150of a desired channel depth, where the channel depth is the number ofbytes that will be accessed from the physical channel before the addressmoves (e.g., rolls, increments, or crosses) into another physicalchannel. The channel depth may reflect the desired performance pointand/or the desired power profile of the requesting application 160. Thechannel depth can be selected based on a desired balance between powerand performance requirements according to various embodiments, asdescribed in more detail below.

In some embodiments, the OS 150 may access a memory unit in which isstored the desired channel depth of the application 160. In someembodiments, the application 160 may notify the OS 150 of its desiredchannel depth. In further embodiments, the OS 150 may learn, for examplethrough gathering of measurement data related to application 160performance, optimal channel depths for the application 160. The OS 150may then store the desired channel depth such that it is associated withthe region mapped to that application 160. As will be described below,the memory controller 115 will use the channel depth for the region todetermine how to handle accesses to memory in the region. Becauseregions are mapped as multiples of OS pages, the minimum region sizeequals the size of one OS page. Additionally, the OS page is the minimumgranularity with which the memory controller 115 will be able to controlchannel depth in the operations described below.

In an embodiment, the memory controller 115 may redundantly maintain twomap RAMs (not shown). The OS 150 may examine and program one of the mapRAMs 140 while the memory controller 115 may use the other map RAM (notshown) for controlling transactions on memory cells of the memory system125. At such a time as the OS 150 has programmed starting and endingaddresses and an associated channel depth for a new region, the OS 150may notify the memory controller 115 that an updated map RAM 140 isavailable, and the memory controller 115 may then switch to using theupdated map RAM 140.

Referring to FIG. 3, while the figure illustrates regions of contiguousOS pages, OS pages within a region need not be contiguous. For example,an OS page in region 310 could be located at any lower available row,for example row 11, while other OS pages in region 310 are located atrows 0 and 1. Methods according to embodiments described herein operateaccording to similar principles regardless of whether the OS pageswithin a region are contiguous.

Regions thus having been mapped to applications 160 and applicationperformance points, the memory controller 115 controls access to memorywithin the regions based on the region definitions in the table in theat least one map RAM 140, such as according to the channel depthsassociated with each region. An application 160 may access the memorysystem 125, via the processor 110 and under control of the memorycontroller 115, according to the method illustrated in FIG. 5.

In operation 500, the memory controller 115 receives a request foraccess to the memory system 125. The request for access includes alogical memory address of the requesting application 160. The requestfor access may be a request to perform a transaction, such as a readoperation or a write operation, upon a memory cell(s) of the memorysystem 125. The logical memory address may be configured according to aparticular addressing method, depending on the manner in which theregions are configured. Example addressing methods are described belowwith respect to FIGS. 6 and 7.

A first example addressing method is described with respect to FIG. 6.In one example embodiment, region sizes may be fixed in the memorysystem 125 hardware, at the time the memory system 125 is manufactured.The regions may be fixed to be the same size, or the regions may befixed to be different sizes. In the illustrative example, the regionseach comprise four OS pages (e.g., four rows of memory cells) in each ofthe physical channels 210-1 through 210-8. Therefore, the row numbers ateach region are known and the region being addressed can be inferredbased on the row numbers, typically the upper bits in the logical memoryaddress 500. The memory controller 115 then looks up the channel depththat was defined for that region when the OS 150 mapped the region tothe application 160. In an example, the memory controller 115 examines atable stored in map RAM 140 (see FIG. 1) to look up the correspondingchannel depth.

In a second example addressing method shown in FIG. 7, the regions maynot be fixed and may or may not be equally sized or symmetric. Instead,the region size may be determined when, for example, the OS 150 requestsallocation of memory on behalf of, for example, application 160. The OS150 may include region identification bits that identify the region towhich the application 160 is mapped. The memory controller 115 looks upthe channel depth, defined for that region when the region was mapped tothe application 160, based on the region identification bits in thelogical address. In an illustrative example, the memory controller 115examines a table stored in a map RAM 140 (see FIG. 1), where the tableassociates a region (e.g., as identified by region identification bits)to a desired channel depth for that application 160.

Referring again to FIG. 5, in operation 510, the memory controller 115retrieves, from the map RAM 140, a channel depth associated with aregion that corresponds to the received logical address. As previouslydescribed, the region is distributed across the two or more physicalchannels 210-1 through 210-8 to include respective portions of the twoor more physical channels 210-1 through 210-8, and the portions arelocated at a same position within each of the one or more physicalchannels 210-1 through 210-8. The memory controller 115 then performs anoperation on the memory system in operation 520, starting at a memorycell in the region corresponding to the logical memory address, based onthe defined channel depth for that region. Operation 520 is described infurther detail in the following paragraphs, with reference to FIG. 3.

Referring again to FIG. 3, each region in a multi-channel memory systemcan have a different channel depth. As previously described, eachregion's channel depth is stored in map RAM 140 such that each channeldepth is associated with the channel depth's corresponding region.Channel depth can be defined as the number of bytes that will beaccessed from the channel before the address moves (e.g., rolls,increments, or crosses) into another channel. In embodiments, theregion's associated channel depth will determine how the region'sinterface will appear to the application 160 mapped to the region. Forexample, if the region's channel depth is 8 bytes, then operation 520accesses all eight physical channels in parallel such that the memorysystem appears to have an x64 interface as in region 320 of FIG. 3. Inthis illustrative example, the requesting application 160 may be anapplication requiring low latency and high performance because of thelarge number of channels operating in parallel. Shallower channel depthsmay therefore be requested for applications requiring low latency.

On the other hand, applications that are latency-insensitive may requestdeeper channel depths, which results in narrower interfaces. If thechannel depth is to be 16 bytes, then operation 520 will access fourphysical channels in parallel such that the memory system appears tohave an x32 interface. As an illustrative example, region 310 of FIG. 3is mapped to an application with a 16-byte channel depth. As shown bythe arrows, starting at the right end of OS Page 0, memory access startsat the right, and trends toward the left. If the region rows were notmapped contiguously, the OS 150 will have kept track of the startingaddress for the next row, and access will proceed at that next row atthe appropriate point. At the end of Row 0, access moves immediatelydown to Row 0 and proceeds from left to right. The four physicalchannels that will be accessed will depend on the logical address forthe transaction that the memory controller 115 received during theaccess request of operation 400.

Similarly, if the channel depth is to be 32 bytes then two physicalchannels will be accessed in parallel such that the memory systemappears to have an x16 interface. The two physical channels that will beaccessed will depend on the address of the transaction, with accessproceeding according to the directional arrows of FIG. 3. Finally, ifthe channel depth is to be 64 bytes, then one physical channel at a timewill be accessed so that the memory system 125 appears to have an x8interface. The physical channel to be accessed will depend on theaddress of the transaction.

Application latencies may be reduced as channel depths become shallowerand more physical channels are accessed in parallel. On the other hand,power requirements may be increased with shallower channel depths.Therefore, deeper channel depths may be preferred to reduce powerconsumption for applications that can accept more latency.

FIG. 8 is a flow diagram illustrating a method of allocating memory in amemory system 125 according to various embodiments. In operation 800, anOS 150 receives a memory allocation request from an application 160. Inoperation 810, the OS 150 allocates a region in a memory system 125based on the request. As described previously, the memory system 125includes a plurality of physical channels 210-1 through 210-8 within oneor more physical devices. The region is distributed to include a sameportion of each of the plurality of physical channels 210-1 through210-8. The OS 150 writes at least one start physical address andcorresponding end physical address to the map RAM 140 of the memorycontroller 115, corresponding to a number of OS pages comprising aregion, where the number of OS pages comprises sufficient memory tofulfill the memory allocation request of the application 160. The memoryallocation request may include a desired channel depth value for theapplication 160. As previously described, the OS 150 may receive, froman application 160, logical memory addresses for transactions to beperformed on the memory system 125. The logical memory address may beconfigured based on an addressing method described above with respect toFIG. 6-7.

The apparatus of various embodiments includes or can be included inelectronic circuitry used in high-speed computers, communication andsignal processing circuitry, memory modules, portable memory storagedevices (e.g., thumb drives), single or multi-processor modules, singleor multiple embedded processors, multi-core processors, data switches,and application-specific modules including multilayer, multi-chipmodules. Such apparatus may further be included as sub-components withina variety of electronic systems, such as televisions, memory cellulartelephones, personal computers (e.g., laptop computers, desktopcomputers, handheld computers, tablet computers, etc.), workstations,radios, video players, audio players (e.g., MP3 (Motion Picture ExpertsGroup, Audio Layer 3) players), vehicles, medical devices (e.g., heartmonitor, blood pressure monitor, etc.), set top boxes, and others.

The above description and the drawings illustrate embodiments to enablethose skilled in the art to practice the embodiments. Other embodimentsmay incorporate structural, logical, electrical, process, and otherchanges. In the drawings, like features or like numerals describesubstantially similar features throughout the several views. Portionsand features of some embodiments may be included in, or substituted for,those of others. Many other embodiments will be apparent to those ofskill in the art upon reading and understanding the above description.

The Abstract of the Disclosure is provided to comply with 37 C.F.R.§1.72(b), requiring an abstract that allows the reader to quicklyascertain the nature of the technical disclosure. The Abstract issubmitted with the understanding that it will not be used to interpretor limit the claims.

What is claimed is:
 1. A method for accessing a memory system, thememory system including two or more physical channels, the methodcomprising: receiving a request for access, the request including alogical memory address; retrieving a channel depth associated with aregion of the memory system that corresponds to the logical memoryaddress, each region of the memory system distributed across the two ormore physical channels to include at least a respective portion of eachof the two or more physical channels, the respective portions beinglocated at a same position within each of the two or more physicalchannels; and performing an operation on the memory system in the regioncorresponding to the logical memory address, based on the retrievedchannel depth and based on the request for access.
 2. The method ofclaim 1, wherein the logical memory address further comprises at leastone bit for indicating the identity of the region to which the logicalmemory address has been mapped, and the at least one bit is added to thelogical memory address by a processor making the access request.
 3. Themethod of claim 1, further comprising: determining an address within theregion on which to perform the requested operation using the receivedlogical address, a starting physical address stored for the region andan ending physical address stored for the region.
 4. The method of claim1, wherein retrieving a channel depth comprises retrieving a channeldepth value of the region; and wherein performing an operation on thememory system based on the retrieved channel depth comprisesdetermining, based on the channel depth value, a point at which to movea physical address within one of the physical channels to access thephysical address.
 5. The method of claim 4, wherein performing anoperation on the memory system further comprises accessing, in parallel,a respective memory cell from each of a number of the physical channels,the number being based on the channel depth value of the region.
 6. Amethod comprising: receiving a memory allocation request; andprogramming a data structure of a memory controller to include a startaddress and an end address for a region of a memory system based on therequest, the memory system including a plurality of physical channels,each region of the memory system including at least a respective portionof each of the plurality of physical channels.
 7. The method of claim 6,further comprising: receiving a second memory allocation request;examining the data structure to determine a second start address for thesecond memory allocation; and programming the data structure to includethe second start address as the start address for a second region. 8.The method of claim 6, further comprising: receiving a request to accessthe region in the memory system, the request including an address forwhich access is requested; appending at least one region-identifying bitto the address; and communicating the address to a memory controller. 9.The method of claim 6, wherein the request includes a channel depthvalue indicating the number of bytes to be accessed from each of theplurality of physical channels of the memory system before an addressmapped to the region moves into a different physical channel of thesystem, and the region includes a number of rows of the plurality ofphysical channels based on the requirements of the application.
 10. Themethod of claim 9, wherein the channel depth value is based on at leastone of a performance requirement and a power requirement of a processrequesting the memory allocation.
 11. A memory controller for a memorysystem having at least two physical channels, the memory controllercomprising: a memory configured to store a data structure definingregions of the memory system, each region of the memory systemcomprising at least a respective portion of each of the two or morephysical channels.
 12. A system comprising: a memory system having twoor more physical channels, each physical channel including a respectiveplurality of rows of memory cells; a processor configured to map anapplication executing on the processor to a respective region of aplurality of regions of the memory system; and a memory controllerconfigured to store a data structure that defines the plurality ofregions of the memory system, wherein each region of the plurality ofregions of the memory system includes at least a respective portion ofeach of the two or more physical channels.
 13. The system of claim 12,wherein the memory is further configured to store a respective channeldepth value for each of the regions, the channel depth value indicatinga number of bytes to be accessed from each of the two or more physicalchannels before an address mapped to the region moves into a differentphysical channel.
 14. A computer-readable medium comprising instructionsthat, when implemented on a machine, cause the machine to: write a firstaddress and a second address to a memory, the first address and thesecond address representing, respectively, a starting address of aregion of a memory system to be allocated to a software application andan ending address of the region of the memory system, the memory systemincluding two or more physical channels, and wherein each of the regionsincludes at least a respective portion of each of the two or morephysical channels.